1. Field
The present disclosure relates generally to high-speed data communications, and more particularly, to mappers and demappers used in multi-wire, multi-phase polarity encoders and decoders.
2. Background
High-speed interfaces are frequently used between circuits and components of mobile wireless devices and other complex apparatus. For example, certain devices may include processing, communications, storage and/or display devices that interact with one another through communications links. Some of these devices, including synchronous dynamic random access memory (SDRAM), may be capable of providing or consuming data and control information at processor clock rates. Other devices, such as display controllers, may require variable amounts of data at relatively low video refresh rates.
High-speed communications links are often provisioned with multiple parallel connectors. Clock recovery circuits rely on rated or specified transition times for edges on the communications links and variable rise times can lead to inter-symbol interference or tolerances values that limit speeds on the high-speed communications links. Variability in rise times is affected by a variety of conditions, including high run-lengths when the state of a wire does not change, allowing the voltage or current levels in the wire to increase beyond typical operating levels.